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? semiconductor components industries, llc, 2005 october, 2005 ? rev. 10 1 publication order number: cs51033/d cs51033 fast p?ch fet buck controller the cs51033 is a switching controller for use in dc?dc converters. it can be used in the buck topology with a minimum number of external components. the cs51033 consists of a 1.0 a power driver for controlling the gate of a discrete p?channel transistor, fixed frequency oscillator, short circuit protection timer, programmable soft?start, precision reference, fast output voltage monitoring comparator, and output stage driver logic with latch. the high frequency oscillator allows the use of small inductors and output capacitors, minimizing pc board area and systems cost. the programmable soft?start reduces current surges at start up. the short circuit protection timer significantly reduces the p?ch fet duty cycle to approximately 1/30 of its normal cycle during short circuit conditions. features ? 1.0 a totem pole output driver ? high speed oscillator (700 khz max) ? no stability compensation required ? lossless short circuit protection ? 2.0% precision reference ? programmable soft?start ? wide ambient temperature range: ? industrial grade: ?40 c to 85 c ? commercial grade: 0 c to 70 c ? pb?free packages are available pin connections 51033 = device code a = assembly location l = wafer lot y = year w = work week x = continuation of device code x = y or g = pb?free package soic?8 d suffix case 751 1 8 marking diagram v fb gnd v cc c osc cs pgnd v c v gate 1 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information 51033 alywx 1 8
cs51033 http://onsemi.com 2 figure 1. typical application diagram v gate pgnd c osc gnd v c cs v cc v fb cs51033 100 f 0.1 f r b 300 c 2 1.0 f gnd 100 r c 10 r g 0.1 f cs 4.7 h irf7404 d 4 10 c in 100 f 1.5v out @ 3.0 am p d 1 d 2 c 1 0.1 f d 3 1n5818 1n4148 1n4148 c 3 100 f c osc 150 pf r a 1.5 k 0.1 f gnd 3.3v in 1n5821 c 0 100 f c 4 0.1 f u1 note : capacitors c 2 , c 3 , and c 4 , are low esr tantalum caps used for noise reduction. maximum ratings rating value unit power supply voltage, v cc 5.0 v driver supply voltage, v c 20 v driver output voltage, v gate 20 v c osc , cs, v fb (logic pins) 5.0 v peak output current 1.0 a steady state output current 200 ma operating junction temperature, t j 150 c storage temperature range, t s ?65 to 150 c esd (human body model) 2.0 kv package thermal resistance, junction?to?case, r jc junction?to?ambient, r ja 45 165 c/w c/w lead temperature soldering: reflow (smd styles only) (note 1) 230 peak c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. 60 sec. max above 183 c.
cs51033 http://onsemi.com 3 electrical characteristics (specifications apply for 3.135 v cc 3.465, 3.0 v v c 16 v; industrial grade: ?40 c < t a < 85 c; ?40 c < t j < 125 c: commercial grade: 0 c < t a < 70 c; 0 c < t j < 125 c, unless otherwise specified.) characteristic test conditions min typ max unit oscillator v fb = 1.2 v frequency c osc = 470 pf 160 200 240 khz charge current 1.4 v < v cosc < 2.0 v ? 110 ? a discharge current 2.7 v > v cosc > 2.0 v ? 660 ? a maximum duty cycle 1 ? (t off /t on ) 80.0 83.3 ? % short circuit timer v fb = 1.0 v; cs = 0.1 f; v cosc = 2.0 v charge current 1.0 v < v cs < 2.0 v 175 264 325 a fast discharge current 2.55 v > v cs > 2.4 v 40 66 80 a slow discharge current 2.4 v > v cs > 1.5 v 4.0 6.0 10 a start fault inhibit time ? 0.70 0.85 1.40 ms valid fault time 2.6 v > v cs > 2.4 v 0.2 0.3 0.45 ms gate inhibit time 2.4 v > v cs > 1.5 v 9.0 15 23 ms duty cycle ? 2.5 3.1 4.6 % cs comparator v fb = 1.0 v fault enable cs voltage ? ? 2.5 ? v max cs voltage v fb = 1.5 v ? 2.6 ? v fault detect voltage v cs when gate goes high ? 2.4 ? v fault inhibit voltage minimum v cs ? 1.5 ? v hold off release voltage v fb = 0 v 0.4 0.7 1.0 v regulator threshold voltage clamp v cs = 1.5 v 0.725 0.866 1.035 v v fb comparators v cosc = v cs = 2.0 v regulator threshold voltage t j = 25 c (note 2) t j = ?40 to 125 c 1.225 1.210 1.250 1.250 1.275 1.290 v v fault threshold voltage t j = 25 c (note 2) t j = ?40 to 125 c 1.12 1.10 1.15 1.15 1.17 1.19 v v threshold line regulation 3.135 v v cc 3.465 ? 6.0 15 mv input bias current v fb = 0 v ? 1.0 4.0 a voltage tracking (regulator threshold ? fault threshold voltage) 70 100 120 mv input hysteresis voltage ? ? 4.0 20 mv power stage v c = 10 v; v fb = 1.2 v gate dc low saturation voltage v cosc = 1.0 v; 200 ma sink ? 1.2 1.5 v gate dc high saturation voltage v cosc = 2.7 v; 200 ma source; v c = v gate ? 1.5 2.1 v rise time c gate = 1.0 nf; 1.5 v < v gate < 9.0 v ? 25 60 ns fall time c gate = 1.0 nf; 9.0 v > v gate > 1.5 v ? 25 60 ns current drain i cc 3.135 v < v cc < 3.465 v, gate switching ? 3.5 6.0 ma i c 3.0 v < v c < 16 v, gate non?switching ? 2.7 4.0 ma 2. guaranteed by design, not 100% tested in production.
cs51033 http://onsemi.com 4 package pin description pin number pin symbol function 1 v gate driver pin to gate of external p?ch fet. 2 pgnd output power stage ground connection. 3 c osc oscillator frequency programming capacitor. 4 gnd logic ground. 5 v fb feedback voltage input. 6 v cc logic supply voltage. 7 cs soft?start and fault timing capacitor. 8 v c driver supply voltage. rg v c v gate pgnd q q r s f2 v gate flip?flop g2 + ? + ? v fb comparator a6 v fb + ? 1.25 v g1 ? + + ? 0.7 v hold off comp + ? fault comp + ? 1.15 v + ? a4 cs charge sense comparator q q r s f1 slow discharge flip?flop + ? gnd g4 g5 ? + a3 slow discharge comparator 2.3 v + ? 2.4 v + ? a2 cs comparator + ? + ? 2.5 v 1.5 v i t 55 i t 5 i t cs g3 c osc + ? + ? 2.5 v 1.5 v a1 v cc oscillator comparator v cc v cc i c 7i c figure 2. block diagram
cs51033 http://onsemi.com 5 circuit description theory of operation control scheme the cs51033 monitors the output voltage to determine when to turn on the p?ch fet. if v fb falls below the internal reference voltage of 1.25 v during the oscillator?s charge cycle, the p?ch fet is turned on and remains on for the duration of the charge time. the p?ch fet gets turned off and remains off during the oscillator?s discharge cycle time with the maximum duty cycle to 80%. it requires 7.0 mv typical, and 20 mv maximum ripple on the v fb pin to operate. this method of control does not require any loop stability compensation. startup the cs51033 has an externally programmable soft?start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output. at startup, the voltage on all pins is zero. as v cc rises, the v c voltage along with the internal resistor r g keeps the p?ch fet off. as v cc and v c continue to rise, the oscillator capacitor (c osc ) and the soft?start/fault t iming capacitor (cs) charges via internal current sources. c osc gets charged by the current source i c and cs gets charged by the i t source combination described by: i cs i t i t 55 i t 5 the internal holdoff comparator ensures that the external p?ch fet is off until v cs > 0.7 v, preventing the gate flip?flop (f2) from being set. this allows the oscillator to reach its operating frequency before enabling the drive output. soft?start is obtained by clamping the v fb comparator?s (a6) reference input to approximately 1/2 of the voltage at the cs pin during startup, permitting the control loop and the output voltage to slowly increase. once the cs pin charges above the holdoff comparator trip point of 0.7 v, the low feedback to the v fb comparator sets the gate flip?flop during c osc ?s charge cycle. once the gate flip?flop is set, v gate goes low and turns on the p?ch fet. when v cs exceeds 2.4 v, the cs charge sense comparator (a4) sets the v fb comparator reference to 1.25 v completing the startup cycle. lossless short circuit protection the cs51033 has ?lossless? short circuit protection since there is no current sense resistor required. when the voltage at the cs pin (the fault ti ming capacitor voltage ) reaches 2.5 v, the fault timing circuitry is enabled. during normal operation the cs voltage is 2.6 v. during a short circuit or a transient condition, the output voltage moves lower and the voltage at v fb drops. if v fb drops below 1.15 v, the output of the fault comparator goes high and the cs51033 goes into a fast discharge mode. the fault timing capacitor, cs, discharges to 2.4 v. if the v fb voltage is still below 1.15 v when the cs pin reaches 2.4 v, a valid fault condition has been detected. the slow discharge comparator output goes high and enables gate g5 which sets the slow discharge flip?flop. the v gate flip?flop resets and the output switch is turned off. the fault timing capa citor is slowly discharged to 1.5 v. the cs51033 then enters a normal startup routine. if the fault is still present when the fault timing capacitor voltage reaches 2.5 v, the fast and slow discharge cycles repeat as shown in figure 3. if the v fb voltage is above 1.15 v when cs reaches 2.4 v a fault condition is not detected, normal operation resumes and cs charges back to 2.6 v. this reduces the chance of erroneously detecting a load transient as a fault condition. figure 3. voltage on start capacitor (v gs ), the gate (v gate ), and in the feedback loop (v fb ), during startup, normal and fault conditions 1.15 v 1.25 v 0 v 1.5 v 2.4 v 2.6 v 2.5 v 0 v v cs v gate v fb start normal operation fault td1 t start t fault t restart td2 t fault s1 s2 s1 s2 s3 s3 s1 s2 s3 s3
cs51033 http://onsemi.com 6 buck regulator operation a block diagram of a typical buck regulator is shown in figure 4. if we assume that the output transistor is initially off, and the system is in discontinuous operation, the inductor current i l is zero and the output voltage is at its nominal value. the current drawn by the load is supplied by the output capacitor c o . when the voltage across c o drops below the threshold established by the feedback resistors r1 and r2 and the reference voltage v ref , the power transistor q1 switches on and current flows through the inductor to the output. the inductor current rises at a rate determined by (v in ? v out )/load. the duty cycle (or ?on? time) for the cs51033 is limited to 80%. if output voltage remains higher than nominal during the entire c osc change time, the q1 does not turn on, skipping the pulse. figure 4. buck regulator block diagram r 1 r 2 c o r load l d 1 feedback control q 1 c in v in charge pump circuit (refer to the cs51033 application diagram on page 2). an external charge pump circuit is necessary when the v c input voltage is below 5.0 v to ensure that there is suf fifient gate drive voltage for the external fet. when v in is applied, capacitors c1 and c2 will be charged to a diodes drop below v in via diodes d2 and d4, respectively. when the p?ch fet turns on, it?s drain voltage will be approximately equal to v in . since the voltage across c1 can not change instantaneously, d2 is reverse biased and the anode voltage rises to approximately 2.0 3.3 v ? vd2. c1 transfers some of its stored charge c2 via d3. after several cycles there is sufficient gate drive voltage.
cs51033 http://onsemi.com 7 applications information designing a power su pply with the cs51033 specifications ? v in = 3.3 v 10% (i.e. 3.63 v max., 2.97 v min.) ? v out = 1.5 v 2.0% ? i out = 0.3 a to 3.0 a ? output ripple voltage < 33 mv. ? f sw = 200 khz 1) duty cycle estimates since the maximum duty cycle d, of the cs51033 is limited to 80% min., it is best to estimate the duty cycle for the various input conditions to see that the design will work over the complete operating range. the duty cycle for a buck regulator operating in a continuous conduction mode is given by: d v out v d v in v sat where: v sat = r ds(on) i out max. in this case we can assume that v d = 0.6 v and v sat = 0.6 v so the equation reduces to: d v out v in from this, the maximum duty cycle d max is 53%, this occurs when v in is at it?s minimum while the minimum duty cycle d min is 0.35%. 2) switching frequency and on and off time calculations f sw = 200 khz. the switching frequency is determined by c osc , whose value is determined by: c osc 95 f sw 1 f sw 3 10 6 30 10 3 f sw 2 470 pf t 1.0 f sw 5.0 s t on(max) 5.0 s 0.53 2.65 s t on(min) 5.0 s 0.35 1.75 s t off(max) 5.0 s 0.7 s 4.3 s 3) inductor selection pick the inductor value to maintain continuous mode operation down to 0.3 amps. the ripple current i = 2 i out(min) = 2 0.3 a = 0.6 a. l min v out v d t off(max) i 2.1 v 4.3 s 0.6 a 15 h the cs51033 will operate with almost any value of inductor. with larger inductors the ripple current is reduced and the regulator will remain in a continuous conduction mode for lower values of load current. a smaller inductor will result in lar ger ripple current. the core must not saturate with the maximum expected current, here given by: i max i out i 2.0 3.0 a 0.6 a 2.0 3.3 a 4) output capacitor the output capacitor limits the output ripple voltage. the cs51033 needs a maximum of 15 mv of output ripple for the feedback comparator to change state. if we assume that all the inductor ripple current flows through the output capacitor and that it is an ideal capacitor (i.e. zero esr), the minimum capacitance needed to limit the output ripple to 50 mv peak?to?peak is given by: c o i 8.0 f sw v 0.6 a 8.0 ( 200 10 3 hz ) ( 33 10 3 v ) 11.4 f the minimum esr needed to limit the output voltage ripple to 50 mv peak?to?peak is: esr v i 50 10 3 0.6 a 55 m the output capacitor should be chosen so that its esr is at least half of the calculated value and the capacitance is at least ten times the calculated value. it is often advisable to use several capacitors in parallel to reduce esr. low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. low impedance aluminum are the cheapest but are not available in surface mount at present. solid tantalum chip capacitors are available from a number of suppliers and offer the best choice for surface mount applications. the capacitor working voltage should be greater than the output voltage in all cases. 5) v fb divider v out 1.25 v r1 r2 r2 1.25 v r1 r2 1.0 the input bias current to the comparator is 4.0 a. the resistor divider current should be considerably higher than this to ensure that there is sufficient bias current. if we choose the divider current to be at least 250 times the bias current this gives a divider current of 1.0 ma and simplifies the calculations. 1.5 v 1.0 ma r1 r2 1.5 k let r2 = 1.0 k rearranging the divider equation gives: r1 r2 v out 1.25 1.0 1.0 k 1.5 v 1.25 200
cs51033 http://onsemi.com 8 6) divider bypass capacitor c rr since the feedback resistors divide the output voltage by a factor of 4.0, i.e. 5.0 v/1.25 v= 4.0, it follows that the output ripple is also divided by four. this would require that the output ripple be at least 60 mv (4.0 15 mv) to trip the feedback comparator. we use a capacitor c rr to act as an ac short so that the output ripple is not attenuated by the divider network. the ripple voltage frequency is equal to the switching frequency so we choose c rr so that: x c 1.0 2 fc is negligible at the switching frequency. in this case f sw is 200 khz if we allow x c = 3.0 then: c 1.0 2 f3 0.265 f 7) soft?start and fault timing capacitor cs cs performs several important functions. first it provides a dead time for load transients so that the ic does not enter a fault mode every time the load changes abruptly . secondly it disables the fault circuitry during startup, it also provides soft?start by clamping the reference voltage during startup to rise slowly and finally it controls the hiccup short circuit protection circuitry. this function reduces the p?ch fet?s duty cycle to 2.0% of the cs period. the most important consideration in calculating cs is that it?s voltage does not reach 2.5 v (the voltage at which the fault detect circuitry is enabled) before v fb reaches 1.15 v otherwise the power supply will never start. if the v fb pin reaches 1.15 v, the fault timing comparator will discharge cs and the supply will not start. for the v fb voltage to reach 1.15 v the output voltage must be at least 4 1.15 = 4.6 v. if we choose an arbitrary startup time of 200 s, we calculate the value of cs from: t cs 2.5 v i charge cs (min) 200 s 264 a 2.5 v 0.02 f use 0.1 f. the fault time out time is the sum of the slow discharge time the fast discharge time and the recharge time and is obviously dominated by the slow discharge time. the first parameter is the slow discharge time, it is the time for the cs capacitor to discharge from 2.4 v to 1.5 v and is given by: t slowdischarge cs ( 2.4 v 1.5 v ) i discharge where i discharge is 6.0 a typical. t slowdischarge cs 1.5 v 10 5 the fast discharge time occurs when a fault is first detected. the cs capacitor is discharged from 2.5 v to 2.4 v. t fastdischarge cs ( 2.5 v 2.4 v ) i fastdischarge where i fastdischarge is 66 a typical. t fastdischarge cs 1515 the recharge time is the time for cs to charge from 1.5 v to 2.5 v. t charge cs ( 2.5 v 1.5 v ) i charge where i charge is 264 a typical. t charge cs 3787 the fault time out time is given by: t fault cs ( 3787 1515 1.5 10 5 ) t fault cs ( 1.55 10 5 ) for this circuit t fault 0.1 10 6 1.55 10 5 0.0155 a larger value of cs will increase the fault time out time but will also increase the soft?start time. 8) input capacitor the input capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on the v cc and v c pins. this capacitor must also ensure that the v cc remains above the uvlo voltage in the event of an output short circuit. c in should be a low esr capacitor of at least 100 f. a ceramic surface mount capacitor should also be connected between v cc and ground to prevent spikes. 9) mosfet selection the cs51033 drives a p?channel mosfet. the v gate pin swings from gnd to v c . the type of p?ch fet used depends on the operating conditions but for input voltages below 7.0 v a logic level fet should be used. choose a p?ch fet with a continuous drain current (i d ) rating greater than the maximum output current. r ds(on) should be less than r ds
0.6 v i out(max) 167 m the gate?to?source voltage v gs and the drain?to?source breakdown voltage should be chosen based on the input supply voltage. the power dissipation due to the conduction losses is given by: p d i out 2 r ds(on) d the power dissipation due to the switching losses is given by: p d 0.5 v in i out ( t r r t f ) f sw where t r = rise time and t f = fall time .
cs51033 http://onsemi.com 9 10) diode selection the flyback or catch diode should be a schottky diode because of it?s fast switching ability and low forward voltage drop. the current rating must be at least equal to the maximum output current. the breakdown voltage should be at least 20 v for this 12 v application. the diode power dissipation is given by: p d i out v d ( 1.0 d min ) ordering information device operating temperature range package shipping ? cs51033yd8 ?40 c < t a < 85 c soic?8 98 units / rail cs51033yd8g soic?8 (pb?free) 98 units / rail cs51033ydr8 soic?8 2500 tape & reel cs51033ydr8g soic?8 (pb?free) 2500 tape & reel cs51033gd8 0 c < t a < 70 c soic?8 98 units / rail cs51033gd8g soic?8 (pb?free) 98 units / rail cs51033gdr8 soic?8 2500 tape & reel CS51033GDR8G soic?8 (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
cs51033 http://onsemi.com 10 package dimensions soic?8 nb case 751?07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 cs51033/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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